Today, as Moore's Law approaches its physical limit and the global semiconductor industry competes for the right to speak in the "post-Moore era" technology, the "Software Defined System on Wafer (SDSoW)" proposed by Wu Jiangxing, an academician of the Chinese Academy of Engineering, and the chiplet technology that has attracted much attention in recent years are reconstructing the future of the chip industry with a multi-dimensional innovative attitude.

The concepts of chiplet and SDSoW are easy to confuse. This article will compare them from three levels: technical dimension, ecological pattern, and strategic value, analyze the relationship between the two, and explain why SDSoW is regarded as "the core path for China to change lanes and overtake in the post-Moore era."

At present, my country's semiconductor industry is facing triple pressure of transformation: the shortage of computing power caused by AI big models forces the innovation of chip design paradigm, and the US technology blockade forces China to explore "asymmetric technology route". The reality that 25% of the world's high-performance CPU/GPU has adopted chiplet design further highlights the industrial maturity of modular technology. In this context, SDSoW integrates wafer-level system integration and domain-specific architecture (DSA), not only integrating the advantages of chiplet in yield improvement, process decoupling, and capacity optimization, but also innovatively introduces system-level capabilities such as software-defined interconnection and large-size wafer substrate integration, breaking through traditional physical limitations and achieving "exponential leap in system engineering gain".

Wu Jiangxing, academician of the Chinese Academy of Engineering and director of the National Digital Switching System Engineering Technology Research Center, made a report entitled "The Development Path of Self-Reliant Software-Defined System on Chip" at the third HiPi Forum, pointing out that the software-defined system on chip (SDSoW) is based on system engineering innovation and is expected to solve the "stuck neck" problem faced by my country's integrated circuit field through the ultra-limited innovation model of "wafer-level heterogeneous integration + generative computing architecture".

Technical dimension

Microelectronics-level innovation vs. system engineering perspective

From a technical logic perspective, SDSoW is not a substitute for Chiplet. Instead, it integrates the core elements of Chiplet through system engineering thinking and reconstructs the paradigm of chip design and system integration at a higher dimension.

Transition of technical concepts

Chiplet is essentially based on modularization. It disassembles a single chip into multiple functional core particles and uses advanced packaging technology to achieve heterogeneous integration. Its core goal is to break through the yield limit and design complexity of a single chip through process decoupling and IP reuse. For example, AMD's Zen architecture processor achieves flexible combination by separating computing units and I/O modules. SDSoW, from the perspective of system engineering, proposes the concept of "wafer-level integration", directly assembling core particle prefabricated parts such as core particles, storage, and interconnection through wafer substrates to form a "functional deconstruction-on-wafer reorganization" soft-hard collaborative architecture. This technical path can not only reuse the core particle design of Chiplet, but also realize dynamic reconstruction through software definition, so that a single physical carrier can adapt to diverse scenario requirements.

Generational leap in integration

Chiplet relies on 2.5D/3D packaging technology (such as CoWoS, EMIB) to achieve interconnection between core particles. Although it can improve bandwidth and energy efficiency, it is still limited by the size of the interposer and packaging density. SDSoW upgrades the traditional PCB board-level or substrate-level connection to "on-wafer ligament interconnection" through a wafer-level interconnection network, directly integrating core particles with a complete wafer as a substrate, increasing the interconnection density by 3-5 orders of magnitude while reducing latency and power consumption.

Dimensional differences in architectural innovation

Chiplet focuses on "how to optimize the combination of core particles", and its innovation is still limited to packaging technology and interface standardization (such as UCIe protocol). SDSoW introduces "software-defined" and "generative variable structure computing" architectures, and realizes "one platform, multiple forms" capabilities by dynamically configuring hardware resources. For example, its wafer-level programmable architecture can reconstruct the connection relationship between computing units and storage units in real time according to the needs of scenarios such as AI training and edge inference, breaking the constraints of fixed hardware on algorithm flexibility. The synergistic effect of this architecture innovation and process innovation enables SDSoW to achieve the asymmetric advantage of "second-rate process versus first-rate performance" under the same process.

In summary, the relationship between SDSoW and Chiplet can be summarized as "inclusive dimensionality upgrade": the former, based on chiplet integration, reconstructs the entire chain from physical carrier to system architecture through system engineering thinking, forming an innovative paradigm of "weak process correlation and strong scenario adaptation". This technological level transition not only provides a Chinese solution to break through the process blockade, but also redefines the development direction of integrated circuits in the post-Moore era.

Ecosystem

From closed technology loop to open collaboration

The difference between the ecological patterns of SDSoW and Chiplet is essentially an extension of the difference in technical thinking. The ecological construction of Chiplet is centered on "chiplet reuse" and achieves interoperability of chips from different manufacturers through standardized interface protocols (such as UCIe), but its essence still remains at the level of "microelectronics engineering" collaboration. Although this model can alleviate the pressure of advanced processes, the ecological dominance is still controlled by international giants, and it is difficult for Chinese companies to break through the role of "follower". For example, the Chiplet ecosystem is highly dependent on Western-dominated industrial chain links such as EDA tools and advanced packaging processes, forming a passive situation of "technical closed loop".

In contrast, the ecological construction of SDSoW is based on "system reconstruction" and reshapes industry rules through open source protocols and independent standards. By establishing the "Golden IP Open Source Community" (such as OpenSDSoW), core IPs such as basic interconnection protocols and dynamic controllers are opened, and a variable structure computing tool chain is provided. This open architecture is not only compatible with the chiplet's chiplet reuse technology, but also incorporates EDA, packaging, materials and other links into an autonomous and controllable technical system through wafer-level heterogeneous integration capabilities. For example, SDSoW supports the integration of multiple materials such as silicon-based and compound semiconductors, breaking the limitations of traditional process generations and forming an ecological pattern of "China-defined, global participation". The relationship between the two is like "operating system and application" - SDSoW is the underlying system-level platform, and Chiplet is its callable modular component.

Strategic value

From local improvement to system reconstruction

In terms of strategic value, Chiplet is an "incremental improvement" to deal with the failure of Moore's Law, while SDSoW is a "disruptive innovation" to solve systemic dilemmas. Chiplet improves chip performance through core-grain splitting and advanced packaging, but its essence is still limited by the underlying defects of the von Neumann architecture and cannot solve systemic contradictions such as idle computing power and memory wall. For example, although Chiplet can optimize single-chip design, the communication delay and energy consumption problems of multi-die interconnection still restrict system-level performance.

The strategic value of SDSoW is reflected in three breakthroughs:

• First, through wafer-level system integration and software-defined architecture, the process technology shortcomings are transformed into non-critical contradictions, realizing asymmetric competition of "second-rate process, first-rate performance". 

• Second, reconstruct the industrial chain with system engineering thinking, promote the full-chain upgrade of EDA tools, packaging technology, and material science, and form a technical closed loop of "algorithm-architecture-carrier" collaborative innovation. 

• Third, build international standard discourse power through open source ecology, such as mathematical description of dynamically reconfigurable architecture, wafer-level operating system and other core technology standards, to provide a carrier for China's transformation from a "rule follower" to a "rule maker".

This strategic leap will not only break through the technological blockade, but also open up a new trillion-level track in the fields of intelligent computing, 6G communications, etc. SDSoW needs to promote the trinity development of "scenario openness + system innovation + ecological aggregation" with a system engineering mindset, cultivate a self-reliant and self-reliant "application-algorithm-architecture-physical carrier" collaborative innovation and industrial ecology, and contribute Chinese solutions to the global digital era.

Source: Crystal World, author: Animism