As smaller process nodes become increasingly expensive, chip manufacturing engineers are seeking alternative ways to increase the number of transistors that can be integrated on a single chip. One research team has developed a method similar to traditional chip stacking techniques, which involves adding a layer of microswitches onto a completed chip by attaching the microswitches to the power and signal transmission areas.
Okay, that's a brief overview of the work done by the Department of Electrical Engineering and Computer Science at MIT, the University of Waterloo, and Samsung Electronics.
Traditional CMOS chip manufacturing involves coating and etching repeating layers of different materials onto an ultrapure silicon wafer. The bottom layer, what MIT calls the front end, contains the chip's transistors (or, in the case of DRAM, capacitors).
However, these devices need power to function, and you also need to be able to read and write data to the groups of transistors that make up logic cells, data registers, etc. These devices consist of multiple layers of metals and insulators—the back end.
Theoretically, transistors can have multiple layers, but unfortunately, the materials used are extremely sensitive to heat during manufacturing. Any conventional process would damage the bottom layer when a new layer is coated. Therefore, a research team led by MIT took a different approach and found a solution.
In other words, they applied a new layer of transistors to the back end. But even this wasn't enough to protect the sensitive front end from high temperatures. The researchers solved this problem by using an extremely thin layer (only 2 nanometers thick) of amorphous indium oxide to build additional transistors.
Compared to traditional materials, it requires a much lower application temperature, thus avoiding front-end damage. The team also discovered that a single layer of ferroelectric hafnium zirconium oxide can be used to fabricate memory cells.
What are the end results? This chip has a higher transistor density compared to chips without additional layers. However, don't get too excited yet. This research is still a long way from fully translating it into usable circuits, but all chip architectures start in this way.
We have seen researchers discover a way to stack multiple layers of transistors together, so if future processors can be built using these two techniques along with traditional chip stacking techniques, the limits of transistor density will be significantly broken.
In recent years, Moore's Law has seemed somewhat unstable, but research like this shows that the rumors about its death are unfounded.
New materials for chips
New materials are expected to improve the energy efficiency of microelectronic products
Researchers at MIT have developed a new manufacturing method that allows for the production of more energy-efficient electronics by stacking multiple functional components onto an existing circuit.
In traditional circuits, logic devices that perform computations (such as transistors) and memory devices that store data are built as separate components, forcing data to be transferred back and forth between them, wasting energy.
This new electronic integration platform allows scientists to integrate transistors and memory devices into a compact structure on a semiconductor chip. This not only significantly reduces energy waste but also increases computational speed.
The key to this breakthrough lies in developing a new material with unique properties and a more precise manufacturing method that reduces the number of defects in the material. This allows researchers to create ultra-small transistors with built-in memory that operate faster than state-of-the-art devices while consuming less power than comparable transistors.
By improving the energy efficiency of electronic devices, this new method can help reduce the ever-increasing power consumption of computing, especially for demanding applications such as generative artificial intelligence, deep learning, and computer vision tasks.
"We must minimize the energy consumed by future artificial intelligence and other data-centric computing, because it is simply unsustainable. We need new technologies like this integrated platform to continue advancing this process," said Yanjie Shao, a postdoctoral researcher at MIT and the first author of two papers on these new transistors.
This new technology is described in two papers, one of which is an invited paper, both of which have been presented at the IEEE International Conference on Electron Devices. Senior authors co-authoring the papers with Shao include Jesús del Alamo, Donner Professor of Engineering at MIT's Department of Electrical Engineering and Computer Science (EECS); Dimitri Antoniadis, Ray and Maria Stata Professor of Electrical Engineering and Computer Science at MIT; and other researchers from MIT, the University of Waterloo, and Samsung Electronics.
Standard CMOS (Complementary Metal-Oxide-Semiconductor) chips typically have a front end for fabricating active components such as transistors and capacitors; and a back end, which includes wires and other metal bonds called interconnects for connecting the various components of the chip.
However, some energy is lost when data is transferred between these bonds, and even slight misalignments can affect performance. Stacking active components can shorten data transmission distances, thereby improving chip energy efficiency.
Typically, it is difficult to stack silicon transistors on CMOS chips because the high temperatures required to fabricate additional devices at the front end can damage the existing transistors underneath.
An integration technology was developed
Researchers at MIT have taken a different approach, developing an integration technique that stacks active components on the back end of a chip.
"If we can utilize this back-end platform to add not only interconnects but also additional active transistor layers, this will significantly increase the chip's integration density and improve its energy efficiency," explains Shao.
The researchers achieved this by using a novel material—amorphous indium oxide—as the active channel layer for the back-end transistors. The active channel layer is where the transistor performs its core function.
Due to the unique properties of indium oxide, they were able to "grow" an extremely thin layer of indium oxide on the back end of existing circuits at a temperature of only about 150 degrees Celsius without damaging the front-end devices.
They meticulously optimized the fabrication process to minimize the number of defects in the approximately 2-nanometer-thick layer of indium oxide material.
A transistor needs a small number of defects, namely oxygen vacancies, to conduct, but too many defects will cause the transistor to malfunction. This optimized manufacturing process enabled researchers to produce extremely tiny transistors that operate rapidly and without defects, significantly reducing the extra energy required for switching between on and off states.
Based on this method, they also fabricated integrated memory back-end transistors measuring only about 20 nanometers. To do this, they added a layer of a material called ferroelectric hafnium oxide as the storage element.
These tiny memory transistors switch at speeds of only 10 nanoseconds, pushing the limits of the research team's measuring instruments. Furthermore, the voltage required for this switching speed is far lower than that of similar devices, thus reducing power consumption.
Because the memory transistors are so small, researchers can use them as a platform to study the fundamental physical properties of individual units of ferroelectric hafnium oxide.
Professor Shao stated, "If we can better understand the physical properties of this material, we can apply it to many new fields. It requires very little energy and gives us a lot of flexibility in device design. It really has the potential to open up many new avenues for the future."
The researchers also collaborated with a team at the University of Waterloo to develop performance models for the back-end transistors, an important step before integrating these devices into larger circuits and electronic systems.
Looking ahead, they hope to build upon these demonstrations to integrate back-end memory transistors into a single circuit. They also aim to improve transistor performance and investigate how to more precisely control the properties of ferroelectric hafnium zirconium oxide.
"Now we can build a versatile electronic platform on the back end of a chip, enabling high energy efficiency and a wide variety of functions in very small devices. We have good device architecture and materials, but we need to keep innovating to explore the limits of performance," Shao said.
This work was partly funded by Semiconductor Research Corporation (SRC) and Intel Corporation. Fabrication was carried out at the MIT Microsystems Technology Laboratory and the MIT Center for Nanotechnology.
Source: Compiled from pcgamer
